
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   11:05:20 04/23/2012
-- Design Name:   stack
-- Module Name:   C:/Xilinx92i/Stack/tb_stack.vhd
-- Project Name:  Stack
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: stack
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_stack_vhd IS
END tb_stack_vhd;

ARCHITECTURE behavior OF tb_stack_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT stack
	PORT(
		clk : IN std_logic;
		operation : IN std_logic;
		enable : IN std_logic;
		d_in : IN std_logic_vector(9 downto 0);          
		d_out : OUT std_logic_vector(9 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL operation :  std_logic := '0';
	SIGNAL enable :  std_logic := '0';
	SIGNAL d_in :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL d_out :  std_logic_vector(9 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: stack PORT MAP(
		clk => clk,
		operation => operation,
		enable => enable,
		d_in => d_in,
		d_out => d_out
	);

	
	process_tb : PROCESS
	BEGIN
		enable <= '0';
		----------------------
		assert (enable /= '0')
		SEVERITY note;
		report "PILA NO ACTIVADA";
		----------------------

		wait for 100 ns;
		enable <= '1';
		operation <= '1';
		-----------------------
		assert (enable /= '1' AND operation /= '1')
		SEVERITY note;
		report "PILA ACTIVADA Y EN MODO APILAR";
		-----------------------
		d_in <= "0000000011";
		-----------------------
		assert (d_in /= "0000000011")
		SEVERITY note;
		report "ENTRADA CORRECTA";
		-----------------------
		wait for 100 ns;
		enable <= '0';
		operation <= '0';
		wait for 100 ns;
		--------------------------
		assert (d_out = "0000000011")
		SEVERITY note;
		report "NO SE PRODUCE LA SALIDA CUANDO LA PILA ESTA INACTIVA";
		--------------------------
		enable <= '1';
		-----------------------
		wait for 100ns;
		assert (d_out /= "0000000011")
		SEVERITY note;
		report "LA SALIDA ES CORRECTA CUANDO LA PILA SE ACTIVA Y ESTA EN MODO DESAPILAR Y SE PRODUCE FLANCO SUBIDA EN CLK";
		-----------------------

		wait; -- will wait forever
	END PROCESS;

	clk <= not clk after 50 ns;
	
--	clk_tb: PROCESS
--	BEGIN
--		wait for 50 ns;
--		clk <= '1';
--		wait for 50 ns;
--		clk <= '0';
--		
--	END PROCESS;
END;
